Several techniques are known in the semiconductor industry for providing isolation between transistors. One such method employs an anisotropic etch of a silicon crystal having a &lt;100&gt; orientation. The etched surface is oxidized and deposited with a thick layer of polysilicon to form islands of single crystal silicon. Subsequently, the wafer is inverted, polished and etched back to expose the silicon islands in which the transistors are formed. Problems associated with this technology are grind and etch-back non-uniformity, limited wafer diameter, large device size, device size dependence on isolation depths, and high parasitic AC impedance with polysilicon substrates.
Several other methods exist for transistor isolation. However, these approaches include PN junction isolation and Local Oxidation of Silicon ("LOCOS") isolation. As these isolation methods are designed for bulk silicon material, they are all subject to parasitic interaction with the substrate.
Still a further method for providing dielectric isolation uses a trench implementation filled with a dielectric material. In FIG. 1 of U.S. Pat. No. 4,631,803, a known trench structure is shown. The trench structure illustrated is intended to minimize stress at the interface between the trench and the semiconductor substrate by curving the bottom of the trench.
Moreover, in FIGS. 2 and 3 of U.S. Pat. No. 4,631,803, a trench structure is illustrated. Here, the inventor teaches the formation of a trench directly on a semiconductor substrate. The trench is filled with a silicon dioxide layer 38, followed by a first silicon nitride layer 40, followed by a refill 42 of either undoped polysilicon or silicon oxide. In FIG. 3, a second silicon nitride layer 48 is also employed.
There are several disadvantages to the trench structure of disclosed and illustrated in FIGS. 2 and 3 of U.S. Pat. No. 4,631,803. Firstly, silicon nitride is a brittle film with a high value of intrinsic stress. Further, silicon nitride has a different rate of thermal expansion than silicon, silicon dioxide, as well as polysilicon. As such, the trench arrangement of FIGS. 2 and 3 is prone to defects and generations of dislocations in silicon due to the stress associated with the silicon nitride layer(s).
Moreover, silicon nitride has a higher dielectric constant in comparison with silicon dioxide. Given the potential for parasitic capacitance by the formation of the trench structure, a higher resultant parasitic capacitance value is created.
Furthermore, the teachings of the trench arrangement of FIGS. 2 and 3 also fail to provide a radiation hardened trench substantially immune to flicker noise. This is because the trench structures of FIGS. 1, 2 and 3 are contained in a bulk silicon semiconductor substrate. This allows for PN junction latch-up problems with the substrate under harsh environments, such as, for example, high voltage, high temperature and radiation environments.
In light of the limitations of these known isolation trench designs, a need exists for an isolation trench which is radiation hardened and substantially immune to flicker noise. Further, the semiconductor industry requires an isolation trench which minimizes stress and defect generation in silicon. Further, an isolation trench on an SOI substrate is needed to provide a means for intrinsic gettering on a semiconductor substrate. Complete dielectric isolation is also in demand to minimize noise and latch-up effects under harsh environments. Furthermore, an isolation trench is required which has improved stress related characteristics, and substantially reduced dislocation generation. Additionally, there is a need in the semiconductor industry for an isolation trench having a substantially lower parasitic capacitance and resistance.